`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    08:35:49 11/21/2012 
// Design Name: 
// Module Name:    memoria_juego 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module memoria_juego(clk_i,adre_a_i,adre_b_i,sal_o,write_i,dato_i,read_i,comparar_i,ad_a_i,ad_b_i,turno_i
    );
	 input clk_i,write_i,read_i,comparar_i,turno_i;
	 input [2:0] adre_a_i,ad_a_i;
	 input [2:0] adre_b_i,ad_b_i;
	 input [1:0] dato_i;
	 output [1:0] sal_o;
	 reg [1:0] tablero [7:0][7:0];
	 reg [1:0] sal_o;
	 reg [4:0] i;
	 reg [3:0] j;
	 initial begin
		sal_o=0;
		for (i=0; i< 8; i=i+1)
			for (j=0; j< 8; j=j+1)
				tablero[i][j]=0; 
	 end
	 
	 always @(posedge clk_i)begin
		if (write_i && turno_i)
			tablero[adre_a_i][adre_b_i]<=dato_i;
		else if (read_i && turno_i)
			sal_o<=tablero[ad_a_i][ad_b_i];
		else if (comparar_i && tablero[adre_a_i][adre_b_i]==0 && turno_i) 
			tablero[adre_a_i][adre_b_i]<=2;
		else if (comparar_i && tablero[adre_a_i][adre_b_i]==1 && turno_i)
			tablero[adre_a_i][adre_b_i]<=3;
	 end
	 
endmodule
		